This article is part of my series of projects around Ternary Computing and Processor Design. Click here to see the list of projects of this series.
In this ongoing project, I am implementing a circuit optimizer for my TernaryVerilog tool suite. It takes a circuit file as an input and the goal is to count the number of transistors necessary to build the circuit and estimate the latency between each register2register pair (hence the maximum frequency of the circuit), and then factorize, prune, simplify and modify some parts of the circuits in order to reduce both the number of transistors and the latency.
The number of transistors can be an estimate of the Area of the chip (and by proxy the cost of fabrication and the yield), and the maximum frequency helps us appreciate the Performance of the processor. Hence, this tool is crucial to compare two processors and evaluate the impact of architectural improvements on PPA figures (power-Performance-Area).
As this project needs refactoring and improvement, this article is a Work In Progress. Sorry about that. You can check out my other articles.
This article is part of my series of projects around Ternary Computing and Processor Design. Click here to see the list of projects of this series.
Go back to the list of projects